1. Field of the Invention
The invention relates to a bus control system and a method using the same, and more particularly to a multiplexed bus data transmission control system and a method using the same.
2. Description of the Related Art
Referring to FIG. 1A, a control system for data transmission between two different buses 110 and 115 according to the prior art is shown. Since the bus 110 is multiplexed, it is necessary to have a buffer 125 if data needs to be transmitted from the bus 115 to the bus 110. The time that data are transmitted from the buffer 125 to the bus 110 is controlled by a controller 120. According to a constant critical value, the controller 120 controls the buffer 125 for data transmission. For example, when the amount of data stored in the buffer 125 is larger than the critical value, the controller 120 allows the data stored in the buffer 125 to be transmitted to the bus 110.
Referring further to FIG. 1B, a data transmission control system for a PCI device 135 is shown. In general, the PCI device 135 has a function of delayed transmission. Whether to perform the function of delayed transmission can be controlled using a register 140. Although software can be used to set up the value stored in the register thereby to determine whether to perform the function of delayed transmission, software does not know the condition of data flow on a bus 130. Therefore, there is only two states, a delayed transmission sate and a non-delayed transmission state, for the data transmission control system.
As described above, it is really inflexible for data transmission control in the prior art. That is, no matter how the amount of data flow is, only two states are used to control data transmission for the conventional data transmission control system.
Referring to FIG. 2A, a timing diagram for data package transmissions with critical values=1 and 4 is shown. L1 represents a timing for a data package transmission with a critical value=1 while L4 represents a timing for another data package transmission with a critical value=4. A1, A2, A3 and A4 represent addresses in which data D1, D2, D3 and D4 are stored, respectively. Referring simultaneously to FIGS. 1A and 2A, a package of current data stored in the buffer 125 can be transmitted to the bus 110 each time a corresponding critical value is equal to 1. When the critical value is equal to 1, it means that the latency for transmitting the package of data is one cycle. That is, there is one cycle assigned for transmitting a package of data right after a corresponding address signal ended. When the critical value is 4, the latency for transmitting a package of data is four cycles. That is, there are four cycles assigned for transmitting. four packages of data right after a corresponding address signal ended. Even though the latency of the former is shorter than that of the latter, the band width occupied of the former is larger that that of the latter. That is, the band width is 8 cycles for the critical value=1 while the band width is 5 cycles for the critical value=4.
Referring to FIG. 2B, a timing diagram for data package transmissions on a PCI bus at a delayed transmission state and a non-delayed transmission state, respectively is shown. R represents a timing for a data package transmission at a delayed transmission state. N represents a timing for a data package transmission at a non-delayed transmission state. D represents a signal indicating that data are ready for transmitting. At the delayed transmission state, a PCI device is repeatedly operated until obtaining R3 data. Inversely, at the non-delayed transmission state, the PCI device occupies the PCI bus until receiving data (for example, data N1). As shown in FIG. 2B, the latency (from the cycle 1 to cycle 12) at the non-delayed transmission state is shorter than that (from cycle 1 to cycle 15) at the delayed transmission state. However, the band width occupied of the former is larger than that of the latter.
As described above, this results in an inflexibility because the conventional data transmission control system is performed only at one of the two states or only can be adjusted by software. However, since software does not detect the condition of the data flow on the bus 130, it can not make a proper adjustment. That is, it is almost useless.
In view of the above, the invention is to provide a first multiplexed bus data transmission control system, suitable for a multiplexed bus data flow control. The multiplexed bus data transmission control system includes a multiplexed bus, a first bus, a bus flow monitor, a critical value controller, a transmission control unit. The first bus from which data are transmitted to the multiplexed bus via a data transmission device. The bus flow monitor is used to calculate a busy time or an idle time of the multiplexed bus to obtain a result and to output the result according to a time constant. The critical value controller includes a band width decoder and a critical value decoder. The band width decoder receives the result from the bus flow monitor and outputs a ratio between the result and the time constant to the critical value decoder, and the critical value decoder outputs a corresponding critical value as the output of the critical value controller according to the ratio calculated by the bandwidth decoder. The transmission control unit is used to control the data transmission of the data transmission device according to the critical value output from the critical value controller.
A second multiplexed bus data transmission control system, suitable for a multiplexed bus data flow control, includes a multiplexed bus, a bus flow monitor, a critical value controller and a transmission control unit. The bus flow monitor is used to calculate the data flow of the multiplexed bus and outputting a calculated result according to a time constant. The critical value controller includes a band width decoder and a critical value decoder. The band width decoder receives the result from the bus flow monitor and outputs a ratio between the result and the time constant to the critical value decoder, and the critical value decoder outputs a corresponding critical value as the output of the critical value controller according to the ratio calculated by the bandwidth decoder. The transmission control unit is used to control a data transmission device using the multiplexed bus according to the critical value output from the critical value controller.
A third multiplexed bus data transmission control system, suitable for a multiplexed bus data flow control, includes a multiplexed bus, a bus flow monitor, a critical value controller and a transmission control unit. The bus flow monitor is used to calculate the data flow of the multiplexed bus and outputting a calculated result according to a time constant. The critical value controller is used to receive the calculate result and to output a corresponding critical value according to a ratio of the calculated result and the time constant. The transmission control unit is used to control a data transmission device using the multiplexed bus according to the critical value outputted from the critical value controller.
Moreover, a method for multiplexed bus data transmission control, suitable for a multiplexed bus data flow control and having a plurality of critical values provided, includes the following steps. A busy time or an idle time of the multiplexed bus is calculated to obtain a calculated result for every time constant. A ratio of the calculated result and the time constant is calculated. A corresponding critical value according to the ratio is outputted. A data transmission device using the multiplexed bus is controlled according to the critical value.
As described above, the advantage of the invention is that various transmission ways adopted can be determined to optimize the performance of the multiplexed bus, according to the condition of the data flow.